Delay Faults Testing

Embedded digital blocks and their interconnections have to be verified by at-speed testing to satisfy the quality and reliability of nowadays System-on-Chips (SoCs). Once a chip is fabricated, it must be tested for pre-specified clock frequency and therefore testing has also to cover speed related faults as well as stuck-at faults. Claim for delay fault testing grows with new technologies. The importance of researching the delay fault testing grows rapidly and obviously the results are published separately for individual problems. The purpose of the chapter is to give an introduction to testing the timing malfunctions in digital circuits. The classification of existing basic and advanced delay fault models is presented with advantages and limitations. The latest test application techniques are described for scan-based synchronous and asynchronous circuits.