High-Level Decision Diagram Simulation for Diagnosis and Soft-Error Analysis
High-Level Decision Diagram Simulation for Diagnosis and Soft-Error Analysis
This Chapter addresses the above-mentioned challenges by presenting a holistic diagnosis approach for design error location and malicious fault list generation for soft errors. First, a method for locating design errors at the source-level of hardware description language code using the design representation of high-level decision diagrams is explained. Subsequently, this method is reduced to malicious fault list generation at the high-level. A minimized fault list is generated for optimizing the time to be spent on the fault injection run necessary for assessing designs vulnerability to soft-errors.
CITATION: Raik, Jaan. High-Level Decision Diagram Simulation for Diagnosis and Soft-Error Analysis edited by Ubar, Raimund . Hershey, PA : IGI Global , 2010. Design and Test Technology for Dependable Systems-on-Chip - Available at: https://library.au.int/high-level-decision-diagram-simulation-diagnosis-and-soft-error-analysis