Memory Testing and Self-Repair

Memories are very dense structures and therefore the probability of defects is higher than in the logic and analogue blocks, which are not so densely laid out. Thus, embedded memories as the largest components of a typical SoC - up to 90% of the chip area dominate the yield of the chip. As fabrication process technology makes great progress, the total capacity of memory bits increases and will cause an extension in area investment for built-in self-testing, built-in repairing and diagnostic circuitry. Many test and repair techniques are used in industry but the research results offer new methods and algorithms for improving digital systems testing quality. The purpose of this chapter is to give a summary view of static and dynamic fault models, effective test algorithms for memory fault (defect) detection and localization, built-in self-test and classification of advanced built-in self-repair techniques supported by different types of repair allocation algorithms.