Optimization of Linearity in CMOS Low Noise Amplifier

In this chapter the authors evaluate a new and promising solution to the problem of power consumption based on “optimum gate biasing.” This technique consists in tracking the MOS operating region wherein the third derivation of drain current is zero. The method leads to a significant IIP3 improvement; however, the sensitivity to process drifts requires the use of a specific bias circuit to track the optimum biasing condition.